Currently, multi-bit sigma-delta data converters, including multi-bit sigma-delta analog-to-digital converters (“multi-bit SD-ADCs”) and multi-bit sigma-delta digital-to-analog converters (“multi-bit SD-DACs”) are widely used for high performance audio applications. The primary reason is that multi-bit SD-ADCs and multi-bit SD-DACs can achieve a targeted dynamic range of about 96 dB or more by utilizing design techniques of oversampling, quantization noise shaping, and element mismatch shaping without having strict device matching requirements or having costly post-fabrication trimming processes. Typically, multi-bit SD-ADCs and multi-bit SD-DACs rely on dynamic element matching (“DEM”) techniques to overcome in-band signal-dependent tones and down-folded quantization noise incurred from device mismatches.
FIG. 1 illustrates a block diagram of a multi-bit SD-ADC of the prior art. A multi-bit SD-ADC 100 converts an analog input signal 101 into a digital output signal 110. The multi-bit SD ADC 100 comprises an adder 113, an analog loop filter 102, a multi-bit quantizer 103, a digital decimation filter 104, a dynamic element matching block 106, and a multi-unit-element DAC 108. The multi-bit SD-ADC 100 oversamples its analog input signal 101 at a predefined oversampling ratio (“OSR”), and then subtracts an analog feedback signal 109 from the sampled analog input signal to generate an analog error signal 111. The analog error signal 111 is filtered by the analog loop filter 102 of a predefined order to generate a loop filter output signal 112, which is then quantized by the multi-bit quantizer 103 of (M+1) levels, where M is an integer greater than or equal to two. The quantizer 103 generates an oversampled digital signal V(n) 105. The digital decimation filter 104 of a decimation factor equal to said OSR decimates the oversampled digital signal V(n) 105 to generate the digital output signal 110 of the SD-ADC 100. The combination of the dynamic element matching circuit 106 and the multi-unit-element DAC 108 converts the oversampled digital signal V(n) 105 into the analog feedback signal 109.
FIG. 2 illustrates a block diagram of a multi-bit SD-DAC of the prior art. A multi-bit SD-DAC 200 converts a digital input signal 201 into an analog output signal 209. The multi-bit SD DAC 200 comprises a digital interpolation filter 202, a multi-bit digital sigma-delta modulator 204, a dynamic element matching block 206, and a multi-unit-element DAC 208. The multi-bit SD-DAC 200 first receives the digital input signal 201, and then interpolates the digital input signal 201 with the digital interpolation filter 202 to generate an interpolated digital signal U(n) 203, where the interpolation factor is equal to the OSR of the SD-DAC 200. The interpolated digital signal U(n) 203 is then quantized by the multi-bit digital sigma-delta modulator 204 of (M+1) levels, where M is an integer greater than or equal to two, to generate an oversampled digital signal V(n) 205. The multi-bit digital sigma-delta modulator 204 also shapes the quantization noise at the same time. The dynamic element matching block 206 and the multi-unit-element DAC 208 then convert the oversampled digital signal V(n) 205 into the final analog output signal 209.
The multi-unit-element DACs 108 and 208 use M unit elements to convert their respective thermometer-coded input control signals 107 and 207 into equivalent analog outputs 109 and 209, where each unit element acts as a unit-weight, e.g., a 1-bit sub-DAC. When a control signal SVk(n)=1 for k=1, 2, . . . , M, its corresponding unit element #k is selected (or activated) to contribute a fraction of 1/M to the multi-unit-element DAC's analog output. When a control signal SVk(n)=0 for k=1, 2, . . . , M, its corresponding unit element #k is deselected (or deactivated) to make no contribution to the multi-unit-element DAC's analog output.
Usually the unit elements of the multi-unit-element DACs 108 and 208 are designed with capacitors, resistors, or current source cells of equal value, in order to achieve a linear DAC transfer curve. However, device mismatches for the unit elements are inevitable in current integrated circuits chip fabrication processes, which causes the unit elements to contribute different values under normal working conditions. As a result, the linearity of the multi-unit-element DAC is impaired, necessitating the use of a dynamic element matching (“DEM”) technique to overcome the element mismatch problem.
The DEM techniques attempt to make the long-term average use rate of each unit element in the multi-unit-element DAC the same, so that the average DAC transfer curve becomes more linear. To achieve this goal, the DEM techniques translate the respective oversampled digital signals V(n), whose value indicates how many unit elements should be selected, into an equivalent set of 1-bit control signals according to a predefined scheme, to get the unit elements selected in a pattern that can shape mismatches.
A prior art DEM technique called the data-weighted-averaging (“DWA”), disclosed by R. T. Baird and T. S. Fiez in the article of “Linearity enhancement of multi-bit delta-sigma A/D and D/A converters using data weighted averaging,” IEEE Transactions on Circuits and Systems: Analog and Digital Signal Processing, vol. 42, pp. 753-762, December 1995, tries to make the long-term average use rates of all the unit elements the same by rotating the element usage pattern sequentially. However, the DWA technique only shapes the element mismatches to the first order, which limits the available improvement in the linearity of the multi-unit-element DAC. Moreover, for input signals of certain amplitudes, DWA is trapped in a periodical use of the unit elements, which incurs mismatch-induced signal-dependent tones in the analog output of the multi-unit-element DAC.
Another prior art DEM circuit 300, disclosed by John Laurence Melanson in the U.S. Pat. No. 6,384,761, is illustrated in FIG. 3. The DEM circuit 300 attempts 2nd-order mismatch shaping. Here, the usage histories of the unit elements are integrated with a plurality of 2nd-order low-pass digital filters 301. A vector quantizer 303 processes the filter outputs 309 and an oversampled digital input signal V(n) 304, which indicates how many unit elements should be selected digital-to-analog conversion. Firstly, the filter outputs 309 are reordered, then control signals SV(n) 305 are generated by the vector quantizer 303 to select the unit elements corresponding to the smallest V(n) filter outputs 309.
Second-order mismatch shaping can improve the linearity of the multi-unit-element DAC effectively. However, the DEM circuit 300 suffers from a stability problem since the integration results of the usage histories for the unit elements are unbounded. In particular, the integration results can keep increasing as time progresses during the digital-to-analog conversion. The key cause of the instability of the DEM circuit 300 is that its digital filters 301 directly integrate the unit element usage histories, whose long-term averages are non-zero and keep on increasing. The unbounded state variables for the digital filters 301 are especially problematic since the digital filters 301 are implemented by fixed-point arithmetic.
In order to make the state variables of the digital filters 301 bounded, a searching-for-minimum block 306 is added, which increases design complexity and implementation cost. However, the state variables of the digital filters 301 can still be found to overflow for some large input signals, which require using large word lengths and/or clip blocks 307 and 308 in the digital filters 301. Consequently, increased implementation costs and degraded mismatch shaping occur in this design.
For the foregoing reasons, there is a need for new methods and apparatuses for dynamic element matching that can shape the element mismatches to the second order with improved stability, lower design complexity, and lower implementation cost.